Split gate non-volatile memory cells, and arrays of such cells, are well known. For example, U.S. Pat. No. 5,029,130 (“the '130 patent”) discloses an array of split gate non-volatile memory cells. The memory cell is shown in FIG. 1. Each memory cell 10 includes source and drain regions 14/16 formed in a semiconductor substrate 12, with a channel region 18 there between. A floating gate 20 is formed over and insulated from (and controls the conductivity of) a first portion of the channel region 18, and over a portion of the drain region 16. A control gate 22 has a first portion 22a that is disposed over and insulated from (and controls the conductivity of) a second portion of the channel region 18, and a second portion 22b that extends up and over the floating gate 20. The floating gate 20 and control gate 22 are insulated from the substrate 12 by a gate oxide 26.
The memory cell is erased (where electrons are removed from the floating gate) by placing a high positive voltage on the control gate 22, which causes electrons on the floating gate 20 to tunnel through the intermediate insulation 24 from the floating gate 20 to the control gate 22 via Fowler-Nordheim tunneling.
The memory cell is programmed (where electrons are placed on the floating gate) by placing a positive voltage on the control gate 22, and a positive voltage on the drain 16. Electron current will flow from the source 14 towards the drain 16. The electrons will accelerate and become heated when they reach the gap between the control gate 22 and the floating gate 20. Some of the heated electrons will be injected through the gate oxide 26 onto the floating gate 20 due to the attractive electrostatic force from the floating gate 20. This technique is often referred to as hot electron injection.
The memory cell is read by placing positive read voltages on the drain 16 and control gate 22 (which turns on the channel region under the control gate). If the floating gate 20 is positively charged (i.e. erased of electrons and positively coupled to the drain 16), then there is sufficient capacitive coupling from the control gate 22 to the floating gate 20 to turn on the portion of the channel region under the floating gate 20, and current will flow across the channel region 18, which is sensed as the erased or “1” state. If the floating gate 20 is negatively charged (i.e. programmed with electrons), then the capacitive coupling from the control gate 22 to the floating gate 20 is insufficient to turn on the portion of the channel region under the floating gate 20 which will remain mostly or entirely turned off, and current will not flow (or there will be little flow) across the channel region 18, which is sensed as the programmed or “0” state. Those skilled in the art understand that the terms source and drain can be interchangeable, where the region partially underneath the floating gate can referred to as the source region 14, and the region adjacent the control gate is referred to as the drain region 16, as shown in FIG. 2. FIG. 2 also shows how pairs of memory cells can be formed sharing a single source region 14. Two adjacent pairs of memory cells can be arranged end to end and share a single drain region 16.
FIG. 3 illustrates a conventional array configuration of memory cells 10. The memory cells 10 are arranged in rows and columns. Each column includes pairs of memory cells that are arranged end to end. Each column is commonly referred to as an active region, and adjacent active regions are insulated from each other by insulation material formed in what is commonly referred to as an isolation region. Each row of memory cells includes a word line WL that electrically connects together all the control gates 22 for that row of memory cells. Preferably, the control gates are formed contiguously across the entire row, and constitute the word line WL (i.e. the control gate for each memory cell is that portion of the word line WL that disposed over that memory cell's channel region). Each row of memory cell pairs includes a source line SL that electrically connects together all the source regions 14 for that row of memory cell pairs. The source line can be a continuous diffusion region extending across the active/isolation regions, or can include a separate conductive line that includes periodic contacts to the source regions. Each column of memory cells includes a bit line BL that electrically connects together all of the drain regions 16 for that column of memory cells.
FIG. 3 shows an array of four rows and four columns, with four word lines WL0-WL3, four bit lines BL0-BL3 and two source lines SL0-SL1. However, it should be understood that a memory array having such an architecture would likely include at least hundreds or thousands of rows and columns.
As detailed above, memory cells are erased by placing a high voltage on the control gate. Thus, an entire row of memory cells is erased at one time by applying a high voltage to the row's word line. One limitation of this architecture is that if there is a need to change information stored in just a portion of the row, such as single byte of information, the entire row would have to erased and reprogrammed. There is no ability to erase just a portion of one row of the memory cells.
There is a need for a memory array architecture that allows for selective erasure of just a portion of a row of memory cells.